In the automated design of integrated circuits, signoff (also written as sign-off) checks is the collective name given to a series of verification steps that must pass before the design can be taped out. This implies an iterative process involving incremental fixes across the board in one or more check type and retesting the design. There are two types of sign-off's are there,namely Front-end sign-off and Back-end sign-off. After back-end sign-off the chip will go to Fabrication. After listing out all the features of specification, Verification Engineer will write coverage for those features and finds out bugs and sends back the RTL design to the designer.Bugs means missing of features,errors in design(typo and functional errors)etc.,.When the coverage reaches a maximum% then Verification team will sign it off. Basically by using a methodology like UVM,OVM or VMM, the verification team will develop a reusable environment. Nowadays UVM is getting more popular than others.